1. Field of the Invention
The present invention relates to a scan driver, an organic light emitting display using the same, and a method of driving the organic light emitting display.
2. Discussion of the Related Technology
Various flat panel displays (FPD) having smaller weight and volume compared with cathode ray tubes (CRT) have been developed recently. In particular, of FPDs, the class of light emitting displays have high emission efficiency, brightness, and response speed and large viewing angles.
Light emitting displays can be classified into two categories: (1) organic light emitting displays using organic light emitting diodes (OLEDs) and (2) inorganic light emitting displays using inorganic light emitting diodes. In the first category, the OLED display includes an anode electrode, a cathode electrode, and an organic emission layer. The organic emission layer is positioned between the anode electrode and the cathode electrode where it emits light by a combination of electrons and holes. In the second category, the inorganic light emitting diode referred to as a light emitting diode (LED) includes an emission layer formed of inorganic material such as a PN-junction semiconductor, as opposed to the organic emission layer of the OLED.
FIG. 1 schematically illustrates the structure of a conventional scan driver for a display composed of OLED pixels.
Referring to FIG. 1, the conventional scan driver includes a shift register 10 and a signal generator 20. The shift register 10 sequentially shifts a start pulse received from an external source in response to a clock signal CLK to generate sampling pulses. The signal generator 20 generates scan signals and emission control signals in response to the sampling pulses supplied from the shift register 10, the start pulse SP, and an output enable signal OE supplied from an external source.
The shift register 10 includes n (where ‘n’ is a natural number) D flip-flops (DF). Here, the D flip-flops DF1 to DFn are driven when the clock signal CLK and the sampling pulses (or the start pulse) are supplied from the outside. The odd D flip-flops DF1, DF3, . . . are driven at the rising edge of the clock signal CLK and the even D flip-flops DF2, DF4, . . . are driven at the falling edge of the clock signal CLK. That is, in the conventional shift register 10, the D flip-flops driven at the rising edge and the D flip-flops driven at the falling edge are alternately arranged.
The signal generator 20 includes a plurality of logic gates. Specifically, the signal generator 20 includes n NAND gates provided in scan lines S1 to Sn, respectively, and n NOR gates provided in emission control signal lines EM1 to EMn, respectively.
The kth (where ‘k’ is a natural number less than or equal to n; k≦n) NAND gate NANDk is driven by the output enable signal OE, the sampling pulse of the kth D flip-flop DFk, and the sampling pulse of the k−1th D flip-flop DFk−1. Here, the output of the kth NAND gate NANDk is supplied to the kth scan line Sk via at least one inverter IN and buffer BU.
The kth NOR gate NORk is driven by the sampling pulse of the k−1th D flip-flop DFk−1 and the sampling pulse of the kth D flip-flop DFk. Here, the output of the kth NOR gate NORk is supplied to the kth emission control line, EMk via at least one inverter IN.
FIG. 2 illustrates waveforms that describe a method of driving the conventional scan driver illustrated in FIG. 1.
Referring to FIG. 2, the clock signal CLK and the output enable signal OE are externally supplied to the scan driver. Here, the period of the output enable signal OE is twice the frequency of the clock signal CLK, and the high voltage periods of the output enable signal OE overlap with the high voltage periods of the clock signal CLK. The output enable signal OE is supplied to control the width of the scan signals SS. Consequently, the width of the scan signals SS is equal to the width of the high voltage period of the output enable signal OE.
When the clock signal CLK is supplied to the shift register 10 and the output enable signal OE is supplied to the signal generator 20, the start pulse SP is externally supplied to the shift register 10 and the signal generator 20.
Specifically, the start pulse SP is supplied to the first D flip-flop, DF1, the first NAND gate NAND1, and the first NOR gate NOR1. The first D flip-flop DF1 that received the start pulse SP is driven at the rising edge of the clock signal CLK to generate a first sampling pulse SA1. The first sampling pulse SA1 generated by the first D flip-flop DF1 is supplied to the first NAND gate NAND1, the first NOR gate NOR1, the second D flip-flop, DF2, and the second NAND gate NAND2.
The first NAND gate NAND1, which received the start pulse SP, the output enable signal OE, and the first sampling pulse SA1, outputs a low voltage when all three supplied signals have a high voltage. Specifically, the first NAND gate NAND1 outputs a low voltage in a period where the first sampling pulse SA1 and the start pulse SP have a high voltage by a period in which the output enable signal OE has a high voltage. The low voltage output from the first NAND gate NAND1 is supplied to the first scan line S1 via a first inverter IN1 and a first buffer BU1. The low voltage supplied to the first scan line S1 is supplied to pixels as the scan signal SS. In the other cases, the first NAND gate NAND1 outputs a high voltage.
The first NOR gate NOR1 that received the start pulse SP and the first sampling pulse SA1 outputs a high voltage when both supplied signals have a low voltage. However, the first NOR gate NOR1 outputs a low voltage when at least one of the start pulse SP and the first sampling pulse SA1 signals has a high voltage. The low voltage output from the first NOR gate NOR1 is subsequently changed into a high voltage through the second inverter IN2, and then supplied to the first emission control signal line EM1. This high voltage supplied to the first emission control signal line EM1 is supplied to the pixels as an emission control signal EMI.
The conventional scan driver repeats the above processes to sequentially supply the scan signals SS to the first nth scan lines S1 to Sn and to sequentially supply the emission control signals EMI to the first nth emission control lines EM1 to EMn. The scan signals SS sequentially select the pixels and the emission control signals EMI control the emission time of the pixels.
In an organic light emitting display, the width of the emission control signals EMI must be freely controlled regardless of the scan signals SS in order to control the brightness of the pixels. Conventionally, the width of the start pulse SP must be increased in order to increase the width of the emission control signals EMI. However, in this case, it is not possible to generate the desired scan signals SS.
The above explanation will be described in detail with reference to FIG. 3, in which the width of the start pulse SP is increased. The width of the start pulse SP must be increased as illustrated in FIG. 3 in order to increase the width of the emission control signals EMI. This occurs because when the width of the start pulse SP increases, the width of the emission control signal EMI, generated by the first NOR gate NOR1 performing a NOR operation on the start pulse SP and the output of the first D flip-flop DF1, increases. However, in this case, the increase in width of the start pulse SP generates undesired scan signals SS. Since the scan signals SS are generated when the start pulse SP, the first sampling pulse SA1, and the output enable signal OE, all have high voltage in the first NAND gate NAND1, the increase in width of the start pulse SP causes a plurality of low voltages to be output from the first NAND gate NAND1. In other words, a plurality of scan signals SS are generated in one frame 1F so that it is not possible to obtain desired scan signals SS.
When the width of the start pulse SP overlaps about two periods of the clock signal CLK, as illustrated in FIG. 3, a plurality of low voltages are output from the first NAND gate NAND1. In the conventional art, since the plurality of scan signals SS are supplied to each of the scan lines S1 to Sn when the width of the start pulse SP increases, the width of the emission control signals EMI is no more than two periods of the clock signal CLK. Also, when the width of the emission control signals EMI increases, non-emission periods increase so that flicker is generated.